发明名称 Semiconductor device and semiconductor module
摘要 A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.
申请公布号 US9368589(B2) 申请公布日期 2016.06.14
申请号 US201414167053 申请日期 2014.01.29
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Baek Sung-Kweon;Nam Gab-Jin;Kim Jin-Soak;Min Ji-Young;Chung Eun-Ae
分类号 H01L29/66;H01L21/336;H01L29/423;H01L29/78;H01L27/108 主分类号 H01L29/66
代理机构 Lee & Morse, P.C. 代理人 Lee & Morse, P.C.
主权项 1. A semiconductor device, comprising: a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate; and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including: a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region,an insulating capping pattern on the gate electrode,a gate dielectric between the gate electrode and the active region, and between the insulating capping pattern and the active region, andan empty space between the active region and the second part of the gate electrode, wherein the gate electrode includes a lower gate conductive pattern and an upper gate conductive pattern, wherein the lower gate conductive pattern is between the gate dielectric and the upper gate conductive pattern, wherein an upper end portion of the lower gate conductive pattern is at a lower level than an upper surface of the upper gate conductive pattern, and wherein the empty space is directly on the upper end portion of the lower gate conductive pattern, and the insulating capping pattern extends to directly contact the gate dielectric to define a top of the empty space.
地址 Suwon-si, Gyeonggi-do KR