HIDING PAGE TRANSLATION MISS LATENCY IN PROGRAM MEMORY CONTROLLER BY SELECTIVE PAGE MISS TRANSLATION PREFETCH

摘要

Example embodiments hide the page miss translation latency for program fetches. In example embodiments, whenever an access is requested by a CPU, the L1l cache controller (111) does a-priori lookup of whether the virtual address plus the fetch packet count of expected program fetches crosses a page boundary (1614, 1622). If the access crosses a page boundary (1622), the L1l cache controller (111) will request a second page translation along with the first page. This pipelines requests to the μΤLΒ (1501) without waiting for L1l cache controller (111) to begin processing the second page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored (1624) locally in L1l cache controller (111) and used when the access crosses the page boundary.