Semiconductor arrangement having first semiconductor device over first shallow well having first conductivity type and second semiconductor device over second shallow well having second conductivity type and formation thereof

摘要

A semiconductor arrangement and method of formation are provided. A semiconductor arrangement includes a first semiconductor device adjacent a second semiconductor device. The first semiconductor device includes a first gate over a first shallow well in a substrate. A first active area is in the first shallow well on a first side of the first gate. The second semiconductor device includes a second gate over a second shallow well. A third active area is in the second shallow well on a first side of the second gate. The second shallow well abuts the first shallow well in the substrate to form a P-N junction. The P-N junction increases capacitance of the semiconductor arrangement, as compared to a device without such a P-N junction.

主权项

1. A semiconductor arrangement comprising:
a first semiconductor device comprising:
a first gate over a first shallow well formed in a substrate, the first shallow well comprising a first conductivity type;a first active area in the first shallow well on a first side of the first gate; anda second active area in the first shallow well on a second side of the first gate; a second semiconductor device comprising:
a second gate over a second shallow well formed in the substrate, the second shallow well comprising a second conductivity type;a third active area in the second shallow well on a first side of the second gate; anda fourth active area in the second shallow well on a second side of the second gate, a sidewall of the first shallow well abutting a sidewall of the second shallow well; and a third semiconductor device comprising:
a third gate over a third shallow well formed in the substrate, the third shallow well comprising the first conductivity type;a fifth active area in the third shallow well on a first side of the third gate; anda sixth active area in the third shallow well on a second side of the third gate, a second sidewall of the second shallow well abutting a sidewall of the third shallow well, and wherein:
the first active area and the sixth active area are coupled to a first voltage supply;the first gate, the third active area, the fourth active area and the third gate are coupled to a second voltage supply; andthe second active area, the second gate and the fifth active area are coupled to a third voltage supply.