Ferroelectric memory device and timing circuit to control the boost level of a word line

摘要

A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.

主权项

1. A semiconductor memory device, comprising:
a memory cell array configured to include a plurality of memory cells; a word line decoder configured to control selection and a voltage level of a word line connected to each of the memory cells; a time determination signal generation circuit configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined; and a timing circuit configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged, wherein the control of whether or not a selected word line is pre-charged is carried out when, after a write command is output, the write command to write first data is output by setting a potential of a bit line connected to the memory cell to a power supply voltage and setting a potential of a plate line connected to the memory cell to a ground potential, and wherein the control of whether or not a selected word line is pre-charged is carried out when the first data is written after second data that are different from the first data have been written to all of the memory cells.