发明名称 |
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP |
摘要 |
PROBLEM TO BE SOLVED: To provide a cell layout of an SRAM for improving characteristics thereof.SOLUTION: An SRAM is configured so as to include: an integral first active region (AcP1) in which a first transistor (TND1) and a fifth transistor (TNA1) are arranged; a second active region (AcP2) which is separated from the first active region (AcP1) and in which a second transistor (TND2) is arranged; an integral third active region (AcP3) in which a third transistor (TND3) and a sixth transistor (TNA2) are arranged; and a fourth active region (AcP4) which is separated from the third active region (AcP3) and in which a fourth transistor (TND4) is arranged. Driver transistors are divided (TND1 and TND2, and TND3 and TND4) and arranged on different active regions (AcP2 and AcP1, and AcP4 and AcP3).SELECTED DRAWING: Figure 2 |
申请公布号 |
JP2016146504(A) |
申请公布日期 |
2016.08.12 |
申请号 |
JP20160076523 |
申请日期 |
2016.04.06 |
申请人 |
RENESAS ELECTRONICS CORP |
发明人 |
MORIMOTO SHIGEO;MAEDA NORIAKI;SHIMAZAKI YASUHISA |
分类号 |
H01L21/8244;H01L27/10;H01L27/11 |
主分类号 |
H01L21/8244 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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