发明名称 Precision half cell for sub-FEMTO unit cap and capacitive DAC architecture in SAR ADC
摘要 A capacitive device is disclosed, including a first conductor formed on a lower metal layer and coupled to a first terminal. A second conductor is formed on an upper metal layer and a plurality of wires is partitioned into groups, each group including one wire from a respective metal layer. First and second wires of each group are coupled to a second terminal. A third wire of each group, adjacent to the first wire, is coupled to the first conductor. A fourth wire of each group, adjacent to the second wire, is coupled to the second conductor. Fifth wires of a first subset of the groups are coupled to the second conductor and fifth wires of a second subset of the groups are coupled to the first conductor. The fifth wire of each group is adjacent to the first wire and the second wire.
申请公布号 US9418788(B2) 申请公布日期 2016.08.16
申请号 US201514643478 申请日期 2015.03.10
申请人 Apple Inc. 发明人 Srinivas Vijay;Keramat Mansour;Chao Yuan-Ju
分类号 H03M1/66;H01G4/01;H01G4/228;H01G4/38;H01G4/12;H03M1/46 主分类号 H03M1/66
代理机构 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. 代理人 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
主权项 1. A capacitive device, comprising: a first conductor formed on a lower metal wiring layer of a plurality of metal wiring layers, wherein the first conductor is coupled to a first terminal; a second conductor formed on an upper metal wiring layer of the plurality of metal wiring layers; and a plurality of parallel wires partitioned into a plurality of layers, wherein parallel wires included in each layer of the plurality of layers are formed in a respective one of a subset of the plurality of metal wiring layers, wherein the subset of the plurality of metal wiring layers excludes the upper metal wiring layer and the lower metal wiring layer, wherein: a first parallel wire and a second parallel wire of each layer of the plurality of layers is coupled to a second terminal;a third parallel wire of each layer of the plurality of layers is coupled to the first conductor, wherein the third parallel wire is adjacent to the first parallel wire;a fourth parallel wire of each layer of the plurality of layers is coupled to the second conductor, wherein the fourth parallel wire is adjacent to the second parallel wire;a fifth parallel wire of each layer of a first subset of the plurality of layers is coupled to the second conductor, and wherein the fifth parallel wire of each layer of a second subset of the plurality of layers is coupled to the first conductor; andthe fifth parallel wire of each layer of the plurality of layers is adjacent to the first parallel wire and the second parallel wire.
地址 Cupertino CA US