Sample-rate conversion in a multi-clock system sharing a common reference

摘要

A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio. The first and second PLLs operate under a locked condition and share a common reference oscillator. An apparatus includes comprises a clock generator including first and second phase-locked loops (PLLs) and configured to generate first and second clock signals, respectively, and a sample-rate converter configured to convert a first discrete sequence to a second discrete sequence based on a sequence of multiples of a reference ratio. The reference ratio is determined based on a first division ratio of the first PPL and a second division ratio of the second PLL.

主权项

1. A method comprising:
determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL; and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio, wherein the first and second PLLs operate under a locked condition and share a common reference oscillator.