Delay line circuits and semiconductor integrated circuits

摘要

A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

主权项

1. A delay line circuit comprising:
a fine delay unit having an input terminal coupled to an input terminal of the delay line circuit and an output terminal coupled to an output terminal of the delay line circuit through a switch; and a coarse delay unit coupled to the output terminal of the fine delay unit in series, wherein the coarse delay unit is coupled to the output terminal of the delay line circuit through a corresponding one of a plurality of first switches, wherein the fine delay unit comprises a fine delay circuit, and the fine delay circuit comprises:
a first PMOS transistor;a plurality of second PMOS transistors coupled between a power voltage and a source of the first PMOS transistor in parallel, wherein widths of gate features of the second PMOS transistor are equal;at least one third PMOS transistor coupled between the power voltage and the source of the first PMOS transistor, wherein a width of gate features of the at least one third PMOS transistor is smaller than the widths of the gate features of the second PMOS transistors;a second NMOS transistor;a plurality of second NMOS transistors coupled between a ground voltage and a source of the first NMOS transistor, wherein widths of gate features of the second NMOS transistors are equal; andat least one third NMOS transistor coupled between the ground voltage and the source of the first NMOS transistor, wherein a width of gate features of the at least one third NMOS transistor is smaller than the widths of the gate features of the second NMOS transistors.