Power supply bus circuit

摘要

A power supply bus circuit, includes a voltage regulator circuit, and an impedance isolation circuit, and further including one or more voltage adjustment circuits, where the voltage regulator circuit receives a direct current signal, adjusts a voltage of the direct current signal to a first preset voltage, and outputs a direct current signal of the first preset voltage to the impedance isolation circuit; the impedance isolation circuit receives the direct current signal of the first preset voltage, adjusts the direct current signal of the first preset voltage to an alternating current signal, and outputs, by using a transformer, the alternating current signal in an isolated way and converts the alternating current signal that is output in an isolated way to an isolated direct current signal, and outputs the isolated direct current signal to the voltage adjustment circuit.

主权项

1. A power supply bus circuit, comprising:
a voltage regulator circuit; an impedance isolation circuit; and one or more voltage adjustment circuits, wherein the voltage regulator circuit has a first positive electrode input end, a first negative electrode input end, a first positive electrode output end, and a first negative electrode output end, wherein the voltage regulator circuit receives a direct current signal through the first positive electrode input end and the first negative electrode input end, adjusts a voltage of the direct current signal to a first preset voltage, and outputs a direct current signal of the first preset voltage through the first positive electrode output end and the first negative electrode output end, wherein the impedance isolation circuit has a second positive electrode input end, a second negative electrode input end, a second positive electrode output end, and a second negative electrode output end, wherein the second positive electrode input end is connected to the first positive electrode output end of the voltage regulator circuit, and the second negative electrode input end is connected to the first negative electrode output end of the voltage regulator circuit, wherein the impedance isolation circuit receives the direct current signal of the first preset voltage through the second positive electrode input end and the second negative electrode input end, adjusts the direct current signal of the first preset voltage to an alternating current signal, and outputs, by using a transformer, the alternating current signal in an isolated way and converts the alternating current signal that is output in the isolated way to an isolated direct current signal, and outputs the isolated direct current signal through the second positive electrode output end and the second negative electrode output end, wherein the voltage adjustment circuit has a third positive electrode input end, a third negative electrode input end, and a power supply end, wherein the third positive electrode input end is connected to the second positive electrode output end of the impedance isolation circuit, and the third negative electrode input end is connected to the second negative electrode output end of the impedance isolation circuit, wherein the voltage adjustment circuit receives the isolated direct current signal through the third positive electrode input end and the third negative electrode input end, chops the isolated direct current signal according to designated conduction time, converts a chopped electric signal to a power source signal of a constant direct current, and outputs the power source signal through the power supply end, wherein the impedance isolation circuit further has a third controlled end, a fourth controlled end, a fifth controlled end, a sixth controlled end, a seventh controlled end, and an eighth controlled end, wherein the impedance isolation circuit comprises a third N-type metal-oxide-semiconductor (NMOS) transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and the transformer, and wherein a drain of the third NMOS transistor is the second positive electrode input end of the impedance isolation circuit, a source of the sixth NMOS transistor is the second negative electrode input end of the impedance isolation circuit, a source of the eighth NMOS transistor is the second negative electrode output end of the impedance isolation circuit, a dotted end of a second secondary coil of the transformer is the second positive electrode output end of the impedance isolation circuit, a gate of the third NMOS transistor is the third controlled end of the impedance isolation circuit, a gate of the fourth NMOS transistor is the fourth controlled end of the impedance isolation circuit, a gate of the fifth NMOS transistor is the fifth controlled end of the impedance isolation circuit, a gate of the sixth NMOS transistor is the sixth controlled end of the impedance isolation circuit, a gate of the seventh NMOS transistor is the seventh controlled end of the impedance isolation circuit, a gate of the eighth NMOS transistor is the eighth controlled end of the impedance isolation circuit, a source of the third NMOS transistor is connected to a drain of the sixth NMOS transistor and an undotted end of a primary coil of the transformer separately, a drain of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, a source of the fourth NMOS transistor is connected to a drain of the fifth NMOS transistor and a dotted end of the primary coil of the transformer separately, a source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor, a source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor, a drain of the eighth NMOS transistor is connected to an undotted end of the second secondary coil of the transformer, and a dotted end and an undotted end of a first secondary coil of the transformer are connected to a drain of the seventh NMOS transistor and the dotted end of the second secondary coil of the transformer respectively; and the impedance isolation circuit receives a third pulse width modulation (PWM) signal of a first preset duty cycle through the third controlled end and the fifth controlled end separately, receives, through the fourth controlled end and the sixth controlled end separately, a fourth PWM signal that differs from the third PWM signal by half a cycle, receives, through the seventh controlled end, a seventh PWM signal that is inverse to the fourth PWM signal in phase, and receives, through the eighth controlled end, an eighth PWM signal that is inverse to the third PWM signal in phase such that the second positive electrode output end and the second negative electrode output end output an isolated PWM electric signal whose duty cycle is twice the first preset duty cycle.