| 摘要 |
PURPOSE:To simplify the circuit constitution by giving the control to the address decoder output which designates the addresses before and after the address of the n-th address signal via the logic gate. CONSTITUTION:The output of AND gates G0-G6, G8-GA and GC all become 1 in case address signals 2<3>-2<0> which designate register R0 are all zero for example. And at the same time, the signals which designate registers R7, RB, RD and RE all become 1. As a result, registers R1-RE are designated in duplication with the address signal which designates register R0, and the data to be written into R0 is also written into R1-RE. Then the writing to the register to receive the writing originally is duplicated to the registers to receive the subsequent writing thus to be written with the same data. And no designated is given to the preceding registers, and thus the prescribed data is written into each register. |
