| 摘要 |
PURPOSE:To reduce a competition chance with the access side of a large access through-put by generating an access address at intervals from an address number column of the access side of a small access through-put and executing a main memory access. CONSTITUTION:A vector unit VU 5 has the through-put N of four times compared with an extension memory control unit (EMU) 6. An EMU 6 transfers the data of 2KB from a 10000 address to a main memory device MSU, and then, the through-put of the EMU is 1 element/1T, and to improve an access efficiency, the access is executed by four elements/4T, and then, the data of 2KB are equivalent to 64 times of 32 byte access. The access is executed to a MSU 1 in accordance with the prescribed table of the EMU access condition. At such a case, from the relation graph of the logical storage LS and time, the inclination of a VU access and an ENU access goes to be equal. Even when the collision of both accesses occurs temporarily, it is within an LS busy time and the through-put is assured.
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