| 摘要 |
PURPOSE:To prevent the generation of output variation at the time of resetting while high speed action is executing, by making respective stages on master/ slave-sides one stage and by independently determining the output level by a switching means that acts in accordance with a reset signal. CONSTITUTION:The master-side consists of a clocked inverter 1 of a latch circuit and a positive feedback circuit 20, while the slave-side consists of a clocked inverter 8 of the P and Q channel gates 4 and 11 of a latch circuit and a positive feedback circuit 21. And, of both sides, the number of stages between the I/O terminals are made one. Accordingly, the data from a terminal D on the master-side is read in a terminal M accordance with a clock phi and inverse phi, and is accurately outputted to a terminal Q on the slave-side. Because the gate is of one stage, the shifting is of a high speed. On the contrary, when the reset signal R becomes H, a switching transistor TN 3 between the inverter 4 and the grounding is turned on, and the terminal Q is forcively maintained in '0', hence is not influenced by the impulse in the raising of the potential due to the shifting of the clock. Consequently, even if the action is made fast the generation of the output variation at the time of resetting is prevented. |
