| 摘要 |
PURPOSE:To shorten a machine cycle and to improve performance by providing a micro instruction register for holding a micro instruction which controls pre-fetching and is given by a selector in terms of an instruction decoding stage. CONSTITUTION:An instruction address stored in an address register 8 in an instruction fetch cycle is supplied to a buffer memory 2 and a micro instruction buffer 3, and an instruction command to be processed and the micro instruction for controlling preprocessing of the instruction are outputted, whereby the instruction command is set to an instruction register 6. At this time, the micro instruction is selected by a selector 5 and set to a micro instruction register 7. The micro instruction obtained in such a way controls the pre-processing of the instruction command stored in the register 6. If the pre-processing of the instruction requires plural cycles, micro instructions controlling subsequent cycles are so controlled that they can be sequentially read out of the 2nd control memory 4 to the register 7. |
