发明名称
摘要 PURPOSE:To write and read data correctly by applying to a chip selection terminal a signal obtained by AND of a memory selection signal and a synchronizing signal synchronized with machine cycles. CONSTITUTION:In a memory access circuit, the low-order digit signals of address signals outputted from a microprocessor 1 are connected to inputs of addresses 4 and 5 of an address latch type memory 3, and the high-order digit signals are inputted to a decoder which converts the high-order digit signals into corresponding memory selection signals to the memory 3; and the memory selection signals outputted by the decoder and a machine synchronizing signal outputted by the microprocessor 1 are inputted to an AND circuit, whose output is inputted to the chip selection terminal of the address latch type memory 3.
申请公布号 JPS6143791(B2) 申请公布日期 1986.09.30
申请号 JP19810055533 申请日期 1981.04.15
申请人 NIPPON ELECTRIC CO 发明人 YONEHARA AKIHITO
分类号 G06F12/06;G06F12/00;G11C7/22 主分类号 G06F12/06
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