发明名称 SIGNAL DELAYING CIRCUIT
摘要 PURPOSE:To make it possible to delay the first output f1 for T time and to delay the second output f2 for 2T time by adding two signals f1 and f2 to the delay line of delay time T and adding again the second signal f2 to the delay line after frequency conversion. CONSTITUTION:A reproducing luminance signal f1 and a reproducing chrominance component f2 which are inputted to an input terminal 5 are supplied to a 1HCCD delay line 1 through an adding circuit 6. The output of this delay line 1 is added to a LPF2 that transits the luminance signal f1 only and the luminance signal that is delayed 1H is outputted from an output terminal 7Y. Also, the output of the delay line 1 is added to a BPF3 that transits the chrominance component f2 and is frequency-converted to the third signal f2+ or -f0. This third signal is frequency-converted at a multiplication circuit 10 through a BPF4 and is restored to the reproducing chrominance component f2 at a BPF11. Therefore, a double horizontal period delayed chrominance component f2 is obtained at a chrominance component output terminal 7C.
申请公布号 JPS61220585(A) 申请公布日期 1986.09.30
申请号 JP19850061560 申请日期 1985.03.26
申请人 SONY CORP 发明人 FUKUDA TOKUYA;MASUDA ISAO
分类号 H03H11/26;H04N9/78;H04N9/84 主分类号 H03H11/26
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