| 摘要 |
<p>PURPOSE:To enable clock skew to be suppressed, prevent the number of I/O pins from being reduced, and enable a power supply pin and I/O pin to be arranged flexibly by using an I/O buffer cell region as a power supply or a grounding pin and by using a transistor within that region as a transistor for clock driver. CONSTITUTION:A transistor of an I/O buffer cell 4 is used as a clock driver 11 and that region is used as a power supply pin or a grounding pin instead of an I/O pin. Namely, a clock driver 11 is placed under a power supply wire 13/a grounding wire 14 of a power supply pin or a grounding pin region 9, all are formed by a first-layer wiring, and a clock signal is supplied to a flip flop at a region within the chip, thus enabling influence of noise due to operation of the clock driver 11 to be suppressed without reducing the number of I/O pins and a gate array where a clock skew is suppressed is formed.</p> |
