| 摘要 |
<p>PURPOSE:To perform tracing with a virtual/actual address and to reduce the cost of a debugger by indicating the virtual address to an address terminal by an output means in a first bus cycle generated by a control means. CONSTITUTION:Independently of the classification of a requested bus cycle, a signal ASEL is made active and a virtual address output timing terminal VASTB 127 is driven in the first bus cycle. In the first bus cycle, a multiplexer 124 selects a virtual address latch VA 121 as the input because the signal ASEL is active, and the page number of the virtual address is outputted to an external address bus AB 120. Since the terminal VASTB 127 indicates that the virtual address is outputted to the external address bus 120, the virtual address is easily sampled in the second bus cycle if the latch is prepared on the outside of a microprocessor.</p> |
