| 摘要 |
A circuit for digitizing an analog video signal using a sample clock signal having an active sample edge, said analog video signal being characterized by a horizontal sync pulse followed by at least one pixel, comprising a phaselocked loop for receiving said horizontal sync pulse and in response generating said sample clock signal at a frequency N times greater than said horizontal sync pulse, said phase-locked loop including a feedback path having a divider for frequency dividing said sample clock signal by N; a first circuit for detecting said at least one pixel and in response generating at least one modified pixel representing an active region of said at least one pixel; a second circuit for receiving and comparing said sample clock signal and said modified pixel and in response generating a control signal representing a degree of phase difference between said sample clock signal and said modified pixel signal; a programmable delay line having a signal input connected to an output of said divider in said feedback path of the phaselocked loop and having a control input connected to said second circuit for receiving said control signal and in response phase shifting said sample clock signal so that said active sample edge is temporally aligned with said active region of said at least one pixel; and an analog-to-digital converter for receiving said sample clock signal and in response digitizing said analog video signal.
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