发明名称 Computer processor having a pipelined architecture which utilizes feedback and method of using same
摘要 A computer processor that performs operations in a logarithmic number system (LNS) domain includes an input log converter (20), a feedback log converter (303), a first data pipeline (304), a second data pipeline (306), a plurality of processing elements (26a-f) coupled to respective stages of the data pipelines, an inverse-log converter (28), and a programmable accumulator (232) which produces output signals. An instruction, selected from a set of instructions, is decoded by a control unit (235) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.
申请公布号 AU6488096(A) 申请公布日期 1997.03.19
申请号 AU19960064880 申请日期 1996.07.08
申请人 MOTOROLA INC. 发明人 SCOTT EDWARD LLOYD;SHAOWEI PAN;SHAY-PING THOMAS WANG
分类号 G06F7/48;G06F7/49 主分类号 G06F7/48
代理机构 代理人
主权项
地址