| 摘要 |
PROBLEM TO BE SOLVED: To shorten an inspecting time of a multistage frequency dividing circuit by selecting an input signal for a 2nd selected signal input terminal with execution of frequency dividing operation by the frequency dividing means in the specified stage for, at least, equal or more than a half frequency. SOLUTION: A signal selecting means 101 inputs clock signals C102 and C110 to a 1st and 2nd selected input terminals respectively, choices between two, and outputs it to a clock signal C102' from an output terminal. Since an operating state selecting signal S101=H and reset is canceled, even though in the initial state, the clock signal C102'=C102, and since the signal of the data input terminal D of a D flip-flop(DFF) with reset in the signal selecting means 101 is latched by falling of the clock signal C103 being the output of a frequency dividing means at the 3rd stage, it becomes Q=H, it becomes the clock signal C102'=C110. That is, in the clock signal C103, its reference clock is switched at the time, when the clock signal C103 itself performs the operations of rising and falling. |
