发明名称 Method of making an integrated circuit structure with planarized layer
摘要 An integrated circuit structure includes a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.
申请公布号 US5985761(A) 申请公布日期 1999.11.16
申请号 US19960666802 申请日期 1996.06.19
申请人 VLSI TECHNOLOGY, INC. 发明人 SPARKS, ERIC A.;HALL, STACY W.
分类号 H01L21/3105;H01L21/311;H01L21/3213;(IPC1-7):H01L21/44 主分类号 H01L21/3105
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