发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To improve information holding performance for a long period by a memory cell, using a non-volatile storage element. SOLUTION: This circuit has first transistors (PM1a, PM2a), capacity elements (PM1b, PM2b), which are provided with a first capacity electrode coupled to a gate electrode of the first transistor and a second capacity electrode facing opposite to it, a second gate electrode, a second source electrode, and a second drain electrode, and further the circuit is provided with a well voltage adjusting means, in which when the second gate electrode comprises second transistors (DM1, DM2) coupled to the first gate electrode of the first transistor, the second transistor is formed in a well region separated from the first transistor, also, the supply voltage for the well region can be adjusted so that substrate bias of the second transistor is made deeper than substrate bias of the first transistor, and a time for closing to initial threshold voltage is extended.</p>
申请公布号 JP2002015587(A) 申请公布日期 2002.01.18
申请号 JP20000193770 申请日期 2000.06.28
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 ISODA MASANORI;TAKAHASHI TSUGIO;YADORI SHOJI
分类号 G11C16/04;G11C29/00;G11C29/04;(IPC1-7):G11C16/04 主分类号 G11C16/04
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