| 摘要 |
PURPOSE: A structure of a cell array for ferroelectric semiconductor memory and a method for sensing data are provided to improve an operating speed by simplifying the structure of the cell array. CONSTITUTION: The first and the second sense amplifiers(300,310) are installed on bit lines of open bit line type. The first sense amplifier(300) is connected to an upper bit line(BLa1) and a lower bit line(BLb1). The second sense amplifier(310) is connected an upper bit line(BLa2) and a lower bit line(BLb2). The first sense amplifier(300) is arranged at a center portion between ferroelectric main cells(MC1,MC11). The second sense amplifier(310) is arranged at a center portion between ferroelectric main cells(MC2,MC21). The first ferroelectric main cells(MC1,MC11) are connected with the bit lines(BLa1,BLb1) and plate lines(MPL1,MPL2), respectively. The second ferroelectric main cells(MC2,MC21) are connected with the bit lines(BLa2,BLb2) and plate lines(MPL1,MPL2), respectively. A plurality of main cell sections(200,210) are formed with the first and the second ferroelectric main cells(MC1,MC11,MC2,MC21). Each ferroelectric main cell(MC1,MC11,MC2,MC21) is formed with one access transistor(1) and one ferroelectric capacitor(2). A plurality of reference cell portions are formed with a plurality of reference cells(RC1,RC11,RC2,RC21). The reference cells(RC1,RC11,RC2,RC21) are connected with the bit lines(BLa1,BLb1,BLa2,BLb2) and reference plate lines(RPL1,RPL2). Each reference cell(RC1,RC11,RC2,RC21) is formed with one access transistor(1) and one ferroelectric capacitor(3). |
