| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory element which allows data to be output regardless of CAS latency information or clock information, and data-access time to be measured within a short period of time. <P>SOLUTION: This semiconductor memory element which measures the data-access time, has a pipe latch control means for generating a input control signal for controlling the data input-output of a pipe latch means in response to a test mode signal; a pipe latch means for receiving data from a memory cell and passing the data in response to the input control signal, an output control means for generating an output node control signal for controlling the data input-output of the output means in response to the test mode signal; and an output means for controlling the data output from the pipe latch means in response to the output node control signal by synchronizing with a clock by a CAS latency in the case of normal mode, and for passing it without synchronizing with the clock in the case of the test mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
