发明名称 DOUBLE CHANNEL MATCHING CIRCUIT
摘要 <p>Connection topology of input terminals (2), elements (4a, 4b, 4c, 4d) and a load (5) is made as a "7-segment display" applied to numerical display for a calculator or a digital clock and the like. That is, the input terminals (2) are assigned to the uppermost and lowermost segments among three horizontally extending segments, the load (5) is assigned to one of four longitudinal segments, and the elements (4a, 4b, 4c, 4d) are assigned to the three remaining longitudinal segments and one horizontal segment. The elements (4a, 4b, 4c, 4d) are an inductor having inductance of 5.119nH, a capacitor having capacitance of 1.370pF, an inductor having inductance of 8.360nH, and a capacitor having capacitance of 5.942pF, respectively. This circuitry can reduce the total number of elements to 4 and realize low loss property. In addition, as a resonance circuit is eliminated and a scale of a ladder circuit is reduced, highly stable impedance matching is attained.</p>
申请公布号 WO2009028197(A1) 申请公布日期 2009.03.05
申请号 WO2008JP02349 申请日期 2008.08.28
申请人 SANGAWA, USHIO;PANASONIC CORPORATION 发明人 SANGAWA, USHIO
分类号 H03H7/38;H04B1/04 主分类号 H03H7/38
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