| 摘要 |
PROBLEM TO BE SOLVED: To automatically perform more correspondent and proper data reception without continuing bit errors to all the wiring configuration specified by CCITT recommendation I.430. SOLUTION: The detection of a violation is performed by two clocks delaying a transmission clock 124 for a fixed time through a delay circuit 111, data from a first or second sampling part 140 or 113 on the side, where frame synchronism is established, are selectively outputted by a selector control circuit 122, violation rule discriminate signals 110 and 119 generated by two sampling parts 104 and 113 are verified after the establishment of frame synchronism and when violation detection abnormality occurs on the side selected at present and the violation is properly detected on the other side, data on that other side are selectively outputted by the selector control circuit 122. |
