| 摘要 |
PURPOSE:To shorten the time of the test for an internal memory, by making the access control due to a CPU for the internal memory controllable from the external by an input signal from a test pin. CONSTITUTION:A controlling circuit 9 is normally under the control of a CPU1 and controls decoders 4 and 5, an output buffer 6, an input/output buffer 7, and input/output ports 80-8n to control the access to an ROM2 and RAM3. When internal memories are tested, the circuit 9 inhibits the control of the CPU1 by the test signal inputted from a test pin and accesses the ROM2 and the RAM3 by a read signal RD and a write signal WR from the external and address information which is given through input/output ports 80-8n. Read stored contents are transmitted to the external again through ports 80-8n. Thus, the time of the test for internal memories is shortened. An internal bus 10 is used in time division to cope with the extension of the capacity of internal memories. |
