发明名称 FRAME SYNCHRONISING SYSTEM
摘要 PURPOSE:To obtain a suitable frame pulse even under the inferior signal receiving environment, by transferring the internal state of a state control circuit to the initial state, etc. when the threshold value of an output of a correlation detecting circuit being in hunting state continues for a prescribed number of times. CONSTITUTION:When the internal state of the state control circuit 35 is the initial state, the point of time of generation of a pseudo frame pulse appearing at each (n+m)T sec is used as the point of time of observation, in a binary signal series having T sec of clofk period taking the frame constitution of (n+m)-bit length comprising a frame synchronizing pattern of n-bit length and information m-bit length. Further, if the state of the output of the correlation detecting cicuit 34 being below the threshold value is consecutive for N times in the initial state, the internal state of the circuit 35 is transferred into the hunting state. If the state of the output of the circuit 34 being over the threshold value is consecutive for M times in this hunting state, the internal state of the circuit 35 is transferred to the initial state. Then, the counted value of a counter circuit 36 is brought to a prescribed value forcedly, and an output of a duplication inhibiting circuit is used as the normal frame synchronising pulse.
申请公布号 JPS58215841(A) 申请公布日期 1983.12.15
申请号 JP19820099704 申请日期 1982.06.10
申请人 NIPPON DENKI KK 发明人 HIROSAKI BOUTAROU
分类号 H04L7/08;H04J3/06 主分类号 H04L7/08
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