| 摘要 |
The invention relates to a structure for protecting pins of an integrated circuit against electrostatic discharges, especially those which occur when handling the circuit when not supplied with power. In order to confer effective protection without too greatly limiting the voltage applied to the pin (C) to be protected, an arrangement is used with a transistor (M1) with thick gate insulant, which has a drain formed preferably by a lightly doped well of opposite type to that of the substrate. This transistor M1 is kept turned off in normal operating regime by a transistor M2 with thin gate insulant, the gate of which is linked to the power supply Vcc. Voltages up to the reverse breakdown voltage of the well/substrate junction can be applied. When the circuit is not connected, positive discharges are transmitted by capacitive coupling from the drain to the gate (at high impedance) of the transistor M1. The latter then becomes conducting and removes the charges. <IMAGE>
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