| 摘要 |
PURPOSE:To provide the arithmetic processor which can execute an instruction at a high speed even when the instruction has dependency relation. CONSTITUTION:Source operand data outputted from a register file is held in registers 17 and 18. Load data from those register 17 and 18 and a data memory are supplied to selecting circuits 15 and 16 by by-passing. An execution stage includes a computing element which processes the source operand data and a memory access stage includes a computing element 12 which processes data selected by the selecting circuits 15 and 16. The selections by the selecting circuits 15 and 16 are controlled according to the data dependence relation between the data load instruction and arithmetic instruction. The computing element output of the execution stage and the output of the computing element 12 in the memory access stage are selected by a selector 19 according to whether or not there is the dependency relation. The load data from the data memory is supplied to the selector 19. |
