发明名称 |
Phase lock loop locking condition detection |
摘要 |
Previous techniques compared reference and actual phase and then applied the reference to a clock, which could result in instabilities occurring. This problem is overcome with the detection system used as the phase difference is compared to the reference signal after being passed through the clock reference.
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申请公布号 |
FR2773925(A1) |
申请公布日期 |
1999.07.23 |
申请号 |
FR19980009356 |
申请日期 |
1998.07.22 |
申请人 |
FUJITSU LIMITED |
发明人 |
KATAYAMA SATOSHI;DOI TAKEHITO;SAITO SHINJI |
分类号 |
H03L7/18;H03L7/095;(IPC1-7):H03L7/08 |
主分类号 |
H03L7/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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