发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To reduce power consumption at the time of reading operation and under non-selecting state by a method wherein the reading operation is performed by making an MOSFET which supplies a predetermined bias voltage to a selected data line corresponding to the respective memory array or memory block to which the selected data line belongs. CONSTITUTION:As switching MOSFET's Q8-Q10 are in ON state when the level of a selection signal Y1 is high, memory information in two memory MOSFET's connected to data lines D10 and D01 is read out into common data lines CD1 and CD0. The memory MOSFET's which are provided between the selected data line D10 and a common source line CS0 and between the data line D01 and a common source line CS2 are made to be in non-operating state because switching MOSFET's Q6 and Q11 which correspond to the memory MOSFET's are turned OFF. Therefore, the potentials of the data lines D10 and D01 are determined in accordance with the memory information of two respective memory MOSFET's provided between the common source line CS1 and the data line D10 and between the common source line CS1 and the data line D01 respectively.</p>
申请公布号 JPS62249478(A) 申请公布日期 1987.10.30
申请号 JP19860092180 申请日期 1986.04.23
申请人 HITACHI VLSI ENG CORP;HITACHI LTD 发明人 SAKAI KIKUO;SHIBATA TAKASHI;KOBAYASHI ISAMU;MORIUCHI HISAHIRO;OGATA SHINKO
分类号 G11C17/12;H01L21/822;H01L21/8246;H01L27/04;H01L27/10;H01L27/112 主分类号 G11C17/12
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