| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve both of an efficiency of write operation and a reduction of write disturb in a nonvolatile memory. <P>SOLUTION: The nonvolatile memory includes a memory array and a parallel write restriction circuit. The memory array has nonvolatile memory cells, in which a write voltage is applied from a write selection word line according to an address signal in the write operation and also a write current is supplied from a transistor (TR6) switching controlled by a write selection bit line and the parallel write restriction circuit according to logical values of write data. The parallel write restriction circuit restricts the bit lines to which the write current flows in parallel, according to difference in write unit. A sequencer applies the write voltage while successively changing over the range of the plurality of bit lines by reducing the range in several times when the write unit is large and also applies the write voltage in the frequency smaller than the above steps by increasing the range of the plurality of bit lines when the write unit is small. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
