Shared memories for energy efficient multi-core processors

摘要

Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a plurality of processor cores. The multi-core processor further can include a shared register file selectively coupled to two or more of the plurality of processor cores, where the shared register file is adapted to serve as a shared resource among the selected processor cores.

主权项

1. A multi-core processor adapted to share processor resources, comprising:
a plurality of processor cores, including first, second, third, and fourth processor cores, configured in a three-dimensional arrangement on a single integrated circuit that includes a plurality of layers, the first, second, third, and fourth processor cores being located on respective first, second, third, and fourth layers of the plurality of layers; a plurality of shared register files, including first, second, third, and fourth shared registers files configured in another three-dimensional arrangement on the single integrated circuit, the shared register files selectively coupled to the plurality of processor cores that are located on the first, the second, the third, and the fourth layers, wherein:
a number of the plurality of shared register files is different than a number of the plurality of processor cores;the first processor core has a larger top surface die area than the second processor core;the second processor core has a larger top surface die area than the third processor core, and the second layer is located above the first layer;the third processor core has a larger top surface die area than the fourth processor core, and the third layer is located above the second layer;the fourth layer is located above the third layer;the first processor core is configured as a graphics processor unit, and the second processor core is configured as a communications processor unit;the first processor core and the second processor core are configured to operate in parallel through their respective use of the first and second register files in order to concurrently complete a graphics part by the first processor core, and a communications part by the second processor core, of a task being executed by the first and second processor cores;the first and second register files are configured to store and share a process state of the task, so that when the first processor core and the second processor core undergo a context switch, the first processor core and the second processor core are configured to respectively retrieve the process state from the first and second register files;each of the plurality of processor cores comprises an associated L1 cache; andthe associated L1 cache comprises a write-through cache; and a crossbar switch configured to selectively couple any one of the plurality of processor cores to any one of the plurality of shared register files.