| 摘要 |
PROBLEM TO BE SOLVED: To optimize a timing margin.SOLUTION: A design device 100 acquires circuit information 101, and layout data 103 which indicates positions of cells and a wiring between cells which are included in an object circuit obtained by first arrangement processing based on a processing result of first logic synthesis processing based on the circuit information 101 and a first timing margin, and clock tree creation processing. The design device 100 derives a delay value based on the clock wiring between the clock supply source and a register, and the cells, for every register included in the object circuit, based on the layout data 103. The design device 100 performs second logic synthesis processing so that, the delay value based on the clock wiring between the clock supply source and the register and the cells becomes the derived delay value, for every register, based on the circuit information 101, and a second timing margin being smaller than the first timing margin.SELECTED DRAWING: Figure 1 |
