Low-power circuit and implementation for despreading on a configurable processor datapath

摘要

Systems and methods for despreading a received signal are described herein. In one embodiment, a vector processor comprises a plurality of code generators, wherein each code generator is configured to generate a different code corresponding to a different code hypothesis. The vector processor also comprises a plurality of despread blocks coupled to a common input for receiving samples of a signal, wherein each despread block is configured to despread at least a portion of the samples with a different one of the codes to generate respective despreaded samples and to accumulate the respective despreaded samples over a length of the code.

主权项

1. A vector processor, comprising:
a plurality of code generators, wherein each code generator is configured to generate a different code corresponding to a different code hypothesis; a plurality of delay elements coupled in series, wherein the delay elements are configured to shift a code by different time delays to generate a plurality of time-shifted codes, each time-shifted code corresponding to a different time hypothesis; and a plurality of despread blocks configured to receive first samples and second samples of a signal; wherein, in a time-searching mode, the plurality of despread blocks is configured to despread at least a portion of the first samples with each one of the time-shifted codes, and, in a code-searching mode, the plurality of despread blocks is configured to despread at least a portion of the second samples with each one of the different codes generated by the code generators.