发明名称 Accelerated erasure coding system and method
摘要 An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.
申请公布号 US9385759(B2) 申请公布日期 2016.07.05
申请号 US201514852438 申请日期 2015.09.11
申请人 STREAMSCALE, INC. 发明人 Anderson Michael H.
分类号 H03M13/00;H03M13/37;H03M13/13;H04L1/00;G06F11/10;G06F12/02;G06F12/06;H03M13/11;H03M13/15 主分类号 H03M13/00
代理机构 Lewis Roca Rothgerber Christie LLP 代理人 Lewis Roca Rothgerber Christie LLP
主权项 1. A system for accelerated error-correcting code (ECC) processing comprising: a processing core for executing computer instructions and accessing data from a main memory, the processing core comprising at least 16 data registers, each of the data registers comprising at least 16 bytes; one or more non-volatile storage media for storing the computer instructions and the data; and an input/output (I/O) controller for controlling data transfers between the main memory and the non-volatile storage media, wherein the processing core, the non-volatile storage media, the I/O controller, and the computer instructions are configured to implement an erasure coding system comprising: a data matrix for holding original data in the main memory;a check matrix for holding check data in the main memory;an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; anda thread for executing on the processing core and comprising: a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor; anda first sequencer for ordering data accesses through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.
地址 Los Angeles CA US