发明名称 SYNTHESIZER POWER SAVE CIRCUIT
摘要 PURPOSE:To minimize the power consumption of a synthesizer at standby by using a power save control circuit so as to interrupt the input of both frequency dividers at the standby, interrupting the power supply of a prescaler counter and inhibiting its input. CONSTITUTION:A reference frequency inhibiting circuit 25 is provided to the input of a reference frequency divider 21 constituting a synthesizer control circuit 2, an input signal inhibition circuit 27 is provided to the input of a programmable frequency divider 24, phase comparison changeover circuits 26, 28 are provided to the input of a phase comparator 22, a power switch 8 and an input inhibition circuit 9 are provided to the input of a prescaler counter 6 and a power saving phase comparator 29 is provided between the changeover circuits 26, 28 and the prescaler counter input inhibition circuit 9 respectively, and they are controlled by a power save control circuit 20. The power save control circuit 20 interrupts the input to both the frequency dividers at the standby and interrupts the power supply of the prescaler counter and inhibits the input, then no current flows to the prescaler counter 8 and the power consumption of the synthesizer is minimized.
申请公布号 JPS62118640(A) 申请公布日期 1987.05.30
申请号 JP19850257600 申请日期 1985.11.19
申请人 FUJITSU LTD 发明人 TODA YOSHIFUMI;SHOJI TATSUYA;MATSUMOTO YOSHIHIRO
分类号 H03L7/18;H03L7/087 主分类号 H03L7/18
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