SEQUENCE COUNTER CONTROL ARRANGEMENT

摘要

An arrangement for controlling the output information of a sequence counter includes a set of output logic gates responsive to the counter output information for generating sequencing information, a blanking circuit for inhibiting each one of the plurality of logic gates, and a control circuit responsive to counter-advancing signals for energizing the blanking circuit and for permitting the counter to generate the sequencing information after a first predetermined time interval following the energization of the blanking circuit, the control circuit de-energizing the blanking circuit after a second predetermined time interval following the first time interval to permit the gates to respond to a group of signals. Thus, the blanking circuit and the control circuit enable the counter to be advanced to a subsequent sequence state before the output logic gates generate the sequencing information so that the stages of the counter are switched to the next state during the second time interval and thus erroneous sequencing information is prevented from being generated during the transition period between sequence states.