发明名称 TIMING SYNCHRONOUS CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the deterioration of communication performance, which is typical of a symbol error rate characteristic by making an interpolator perform approximating interpolation of the sample value of a desired time from the outputs of a pre-interpolator, that produces digital signals of a specified sampling speed of an inputted digital signal. SOLUTION: An I component and a Q component of a digital signal outputted from an A/D converter are inputted to input terminals 101 and 102 respectively. A pre-inputolator 11 interpolates the sample value of an intimidate time of each sample to the I and Q components and doubles the sampling speed. Input signals from the pre-interpolator 11 to an interloper 12 become signals, whose sampling speed is two times faster. Output signals of the interpolator 12 are outputted from output terminals 161 and 162 and also pass through the feedback path of a timing error detection circuit 13, a loop filter 14 and a control circuit 15 and signals k and μ representing times at which the interpolator 12 conduits interpolation are outputted from the circuit 15.
申请公布号 JPH11243432(A) 申请公布日期 1999.09.07
申请号 JP19980059082 申请日期 1998.02.25
申请人 NEW JAPAN RADIO CO LTD 发明人 ONO SHIGERU
分类号 H04L27/22;H04L7/00 主分类号 H04L27/22
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