| 摘要 |
PURPOSE:To drastically shorten the scan-in and scan-out processing time. CONSTITUTION:A selection signal (d) and a scan-in signal (c) are inputted into an all F/F1a-1d. A scan-out mode signal (b) and the selection signal (d) are inputted into a HAND 5, and the output is inputted into the all F/F1a-1d. In the normal operation, F/F1a-1d set the data (a) in synchronization with a clock signal (f), and the output is inputted into a CMB 2. An ADR 3 decodes an address signal (e) and outputs the address. When the signal (d) is '1' and the signal (b) is '1' for the dF/F selected by the address, the data supplied from the signal (c) is set in synchronization with the clock signal (f), and when the signal (d) is '1' and the signal (b) is '1', only the data of the F/F selected by an ADR 3 is read out and the output of other F/F is suppressed. The outputs of all F/F1a-1d are outputted through an OR 4. |
