发明名称
摘要 <p>PURPOSE: To increase the working efficiency of a line by suppressing delay time by transmitting/receiving by multiplexing a data set less than the pay load of an ATM cell on the cell at every ground. CONSTITUTION: A switching processing part performs connection control in advance, and performs the connection control of the lines (a), (b) and the lines (c), (d) and the decision of a cell header at every call. The controller 701 of a demultiplexing device 401 holds communication by a processing part 103 and a control signal, and performs the connection control of the lines (a), (c) and (d) and the decision of the cell header. The controller 701 holds the communication with the processing part 103, and confirms to which counter node the line (a) should be connected, and allocates the cell inputted from a cell forming device 102 to buffers 704-1 to 704-K at every cell by a switch circuit 702. The cell collected in the buffer 704-j(j=1-h) at every ground is multiplexed on the line allocated at every ground by a multiplex circuit 705-j. The circuit 705-j performs the multiplex processing of communication data accumulated in the buffer 704-j, and transmits it to the counter node.</p>
申请公布号 JP2953647(B2) 申请公布日期 1999.09.27
申请号 JP19940327794 申请日期 1994.12.28
申请人 ENU TEI TEI IDO TSUSHINMO KK 发明人 MORIKAWA HIROMOTO;ISHINO FUMIAKI;KAWAKAMI HIROSHI
分类号 H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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