发明名称 Semiconductor integrated circuit and method for testing the same
摘要 When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.
申请公布号 US6971052(B2) 申请公布日期 2005.11.29
申请号 US20020255671 申请日期 2002.09.27
申请人 FUJITSU LIMITED 发明人 TSUBOI HIROYOSHI;FUJIOKA SHINYA
分类号 G01R31/28;G01R31/3181;G01R31/3185;G11C29/46;H01L21/822;H01L27/04;(IPC1-7):G11C29/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址