High-speed, low-power input buffer memory for use in integrated circuit, has voltage compensation units for inducing voltage compensation between input voltage signal, pull-up transistor and pull-down transistor

摘要

The input buffer memory (200) includes a pull-up transistor and a pull-down transistor that are capacitively connected with an input voltage signal. Voltage compensation units are provided for inducing voltage compensation between the input voltage signal and the pull-up transistor, and between the input voltage signal and the pull-down transistor. An output node is provided between the pull-up transistor and pull-down transistor. The pull-up transistor is provided in the form of P-channel MOS (metal oxide semiconductor) transistor while the pull-down transistor is an N-channel MOS transistor. The pull-up transistor is connected to a first voltage node which provides the supply voltage. The pull-down transistor is switched between the pull-up transistor and second voltage node which supplies ground voltage. An independent claim is included for the operation method of the input buffer memory.