Non-volatile semiconductor memory device and manufacturing method thereof

摘要

This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

主权项

1. A non-volatile semiconductor memory device, comprising:
a memory cell array including NAND cell units arranged therein, the NAND cell unit being configured to extend in a first direction vertical to a surface of a semiconductor substrate, the NAND cell unit being formed by coupling a plurality of memory cells and selection transistors in series; and a local source line formed on the semiconductor substrate, the local source line being electrically coupled to one end of the NAND cell unit, wherein the memory cell array includes:
a laminated body where a plurality of conductive films are laminated sandwiching an interlayer insulating film, the conductive film being a control gate line of the memory cell or a selection gate line of the selection transistor;a semiconductor layer that extends in the first direction; andan electric charge accumulating layer sandwiched between the semiconductor layer and the conductive film, the local source line includes a silicide layer, and the electric charge accumulating layer is continuously formed from the memory cell array to cover a whole of a peripheral surface of the silicide layer.