发明名称 |
Mixed precision fused multiply-add operator |
摘要 |
A circuit for calculating the fused sum of an addend and product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplication operands are in a lower precision format than the addend, with q>2p, where p and q are the mantissa size of the multiplication operand and addend precision formats. The circuit includes a p-bit multiplier receiving the mantissas of the multiplication operands; a shift circuit aligning the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and an adder processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa. |
申请公布号 |
US9367287(B2) |
申请公布日期 |
2016.06.14 |
申请号 |
US201214113636 |
申请日期 |
2012.04.19 |
申请人 |
KALRAY |
发明人 |
Dupont De Dinechin Florent;Brunie Nicolas;Dupont De Dinechin Benoit |
分类号 |
G06F7/38;G06F7/487;G06F7/483;G06F7/544 |
主分类号 |
G06F7/38 |
代理机构 |
Oliff PLC |
代理人 |
Oliff PLC |
主权项 |
1. A method of fused calculation of the sum of an addend and a product of two multiplication operands using a floating-point unit of a proccessor, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent, wherein the multiplication operands are in a lower precision format than the addend, with q>2p, where p is the mantissa size of the multiplication operands precision format and q is the mantissa size of the addend precision format, the method comprising the steps of:
multiplying, using a p-bit multiplier, the mantissas of the multiplication operands; right-padding the 2p-bit product resulting from the multiplication with zeros to form a q-bit product mantissa; aligning, with a shifter, the mantissa of the addend and the mantissa of the product based on the exponent values of the addend and multiplication operands; and adding with an adder, the aligned mantissas of the product and the addend. |
地址 |
Orsay FR |