| 摘要 |
The converter employs a selection network 1 in which the applied binary coded decimal digits are selected in pairs of increasing order of decimal denominational significance to be passed to the address lines of a pair of memory elements 11, 21. The locations of the memory contain the binary terms equivalent to the decimal digits from which the particular location address is derived. The notional capacity of the locations in terms of the number of binary denominations specifiable may be increased by separately generating bits of higher denominational significance, and this separate generation may take the form of a logic gating operation 31 applied either to generate a binary term directly or to re-allocate the denominational significances of bit positions within a location. <IMAGE> |
