| 摘要 |
<p>A memory test circuit is described. The memory test circuit comprises means (12, 13) for simultaneously writing identical test data into several memory cells (14), means (13) for simultaneously reading the test data written into the memory cells, means (16) for obtaining a first logical operation of the test data read from the memory cells, means (17) for obtaining a second logical operation of the test data read from the memory cells, and means (18,19, SW1, SW2) for inspecting whether or not the memory cells into which the test data is written operate correctly is carried out on the basis of the first logical operation and second logical operation of the test data read from the memory cells.</p> |
