| 摘要 |
PURPOSE:To efficiently test a dynamic characteristic at the time of high speed operation even with respect to a high speed large capacity memory integrated circuit, by constituting a testing apparatus of a main control circuit and a peripheral testing circuit. CONSTITUTION:A main control circuit 20 coming to a host side is allowed to perform the indication of a test item or testing mode such as rough sorting or allotment, this is, the selection of test content relating to the test of a memory integrated circuit MUT. A peripheral testing circuit 10 is allowed to perform function successively indicating the peripheral address of the address incidated, that is, aimed at each time by the main control circuit 20 at a high speed. Therefore, the main control circuit 20 may be slow in its operation speed as compared with the memory integrated circuit MUT being a test object and the peripheral testing circuit 10 may substantially deal with only a part of the address outputted by the main control circuit 20 and, therefore, a hardware scale can be reduced and high speed operation becomes possible.
|
