| 摘要 |
The circuit has an internal clock generator (50) which by way of a reference clock, generates a number of accurately mutually time delayed clock signals (56,58). A clock alignment circuit (52) is controlled by incoming serial data (Din). A number of differently phased clock signals are generated the phase positions of which are set in dependence of the phase position of the incoming data. A first demultiplexer (86,88) is arranged to clock incoming serial data to a parallel data flow. - A second demultiplexer is arranged to align by the clock signals, thin data flow to outgoing data in parallel form (D1-D4). A phase corrector (55) with a selector and mixer are provided for mixing the selected clock signals. |
